Breakthrough 3D-Stacked AI Inference Chip Enabling the Deployment of Multi-Billion-Parameter LLMs on Edge Devices

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Large Language Models (LLMs) are at the center of the roadmaps of almost all large tech companies for new features in electronic devices. However, they usually consists of billions of parameter and running them outside the cloud in edge devices limits the chip size often to less than a square centimetre of silicon and less than 1 W continuous power consumption amongst other criteria. Current technologies not just fail to provide these technical features but also lack of the potential to meet these requirements in the future. This includes digital hardware (energy in-efficiency) as well as new compute paradigms (e.g. in-memory computing) that can only run models of few million parameters on such a small footprint. Instead of the expensive and limited technology node scaling, SEMRON is working on a 3D scaled AI inference chip to incorporate LLMs on a tiny footprint without overheating. This is enabled by a new semiconductor technology that was already tested (CapRAM). CapRAM is utilising a capacitive approach instead of the resistive approaches known in other in-memory computing approaches. This approach shows an inherently better signal-to-noise ratio that is necessary to achieve the energy-efficiency that is required to not run into overheating issues when increasing the compute density (3D). With monolithic growth the compute layers are stacked in the semiconductor manufacturing process based on the matured 3D NAND flash approach. This not just provides the ability to stack hundreds of compute layers but also to decrease the costs per performance ratio by two orders of magnitude. SEMRON is building the demonstrator of such monolithically grown 3D AI inference chip based on the CapRAM technology that itself already constitutes a superior AI solution for edge devices.