MIT Vertical Stacked Microelectronics Fabrication

under development

Prospective

Massachusetts Institute of Technology (MIT) researchers have developed a new materials and chip-fabrication approach that enables vertical stacking of electronic components on microchips using a low-temperature method. This approach uses amorphous indium oxide to form ultra-thin transistor layers at around 150 °C, allowing components to be built directly on top of existing circuits without damage. The vertical stacking reduces signal travel distance, cutting energy losses and improving efficiency. The project also demonstrated memory transistors using ferroelectric hafnium–zirconium oxide, enabling compact, low-power memory devices. This innovation aims to enable compute-in-memory architectures and more energy-efficient, high-performance computing.

United States of America (USA)

Massachusetts

ZAWYA

Project

Manufacturing (Industrial), Power Generation (CCGT)