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Robust and Efficient Approaches to Evaluating Side Channel and Fault Attack Resilience

Source: EU Funding & Tenders Portal

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Implementing cryptography on embedded devices is an ongoing challenge: every year new implementation flaws are discovered and new attack paths are being used by real life adversaries. Whilst cryptography can guarantee many security properties, it crucially depends on the ability to keep the used keys secret even in face of determined adversaries. Over the last two decades a new type of adversary

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The project "Robust and Efficient Approaches to Evaluating Side Channel and Fault Attack Resilience" is an infrastructure initiative in the Aerospace & Defense, Power Generation (CCGT), Advanced Electronics, Education, Government sector, located in N/A, Belgium. Taiyo aggregates data from EU Funding & Tenders Portal, including information on sponsoring government bodies, EPCs, and contractors.

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Implementing cryptography on embedded devices is an ongoing challenge: every year new implementation flaws are discovered and new attack paths are being used by real life adversaries. Whilst cryptography can guarantee many security properties, it crucially depends on the ability to keep the used keys secret even in face of determined adversaries. Over the last two decades a new type of adversary has emerged, able to obtain, from the cryptographic implementation, side channel leakage such as recording of response times, power or EM signals, etc. To account for such adversaries, sophisticated security certification and evaluation methods (Common Criteria, EMVCo, FIPS…) have been established to give users assurance that security claims have withstood independent evaluation and testing. Recently the reliability of these evaluations has come into the spotlight: the Taiwanese citizen card proved to be insecure, and Snowden’s revelations about NSA's tampering with FIPS standards eroded public confidence. REASSURE will (1) improve the efficiency and quality of all aspects of certification using a novel, structured detect-map-exploit approach that will also improve the comparability of independently conducted evaluations, (2) cater for emerging areas such as the IoT by automating leakage assessment practices in order to allow resistance assessment without immediate access to a testing lab, (3) deliver tools to stakeholders, such as reference data sets and an open-source leakage simulator based on instruction-level profiles for a processor relevant for the IoT, (4) improve existing standards by actively pushing the novel results to standardization bodies. REASSURE's consortium is ideal to tackle such ambitious tasks. It features two major circuits manufacturers (NXP, IDEMIA), a highly respected side channel testing lab (Riscure), an engaged governmental representative (ANSSI), and two of the most prominent research institutions in this field (UCL, University of Bristol).

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