Topological semimetals for ultra-efficient electrical interconnects

forthcoming

Moore's law dictates that the number of transistors in a Si CMOS integrated circuit will double every other year through size reductions that result in improved devices with smaller footprints. However, smaller transistors and greater transistor density also requires smaller interconnect copper metal wires to connect billions of transistors together. The issue is that metal wires, in contrast to transistors, show degraded performance when reduced in size. This has resulted in an interconnect bottleneck, i.e. the situation when overall circuit performance is determined by interconnect delays, rather than transistor performance, and is one of the most serious challenges facing CMOS scaling today. By 2030, the interconnect linewidth will reach below 10 nm. At that point, Cu shows exponentially increasing resistivity due to surface and grain scattering, which will result in significantly increased delays and power dissipation. The solution to this issue is to develop new interconnect materials with improved properties at technologically relevant dimensions. This is the goal of the TICON project. The long-term vision of TICON is to replace scaled Cu interconnects in CMOS technologies with topological semimetals, a class of materials where electrical currents are dominated by surface states that exhibit protection from scattering. Several experimental reports now exist showing the extraordinary scaling properties of such materials, indicated by a reduction (rather than increase) of resistivity, as the dimensions of the semimetal are reduced. In this project, we employ the latest understanding of the physical mechanisms that govern topological semimetal transport, chirality, correlation and surface state engineering, together with a focused effort to synthesize high-quality thin films. We will then demonstrate the integration of such films on Si platforms, and establish the required material properties and optimizations to facilitate uptake into Si CMOS technology.